1. Field of the Invention
The present invention generally relates to integrated circuits (ICs), and more particularly to a structure and method for forming wiring lines for the integrated circuits and relates to an interconnect scheme forming an additional type of metal lines without additional mask levels.
2. Description of the Related Art
In DRAM circuits, the need for multiple metal levels is driven by the requirement to increase the array efficiency with increasing memory size. Three metal levels are conventionally used as bitline, master or stitched wordline and column select lines.
Recently, several hybrid or hierarchical bitline architectures have been proposed in order to decrease the number of sense amplifiers. These architectures require an additional metal level. Simultaneously, DRAM support circuits also need multiple wiring levels for area reduction. Low resistance is the main requirement for the support circuits, in particular for power bussing.
By the same token, low capacitance is important for the use as bitlines or master bitlines in the array.
Conventional interconnection architecture for integrated circuits typically includes horizontal lines of various materials (e.g., metal silicides, W, Al , Cu, and the like), and vertical vias between the horizontal interconnect levels (e.g., M1, M2 wiring levels which are horizontal).
The vias are typically etched into the interlevel dielectric (ILD) formed, for example, of SiO.sub.2, and subsequently are filled by chemical vapor deposition (CVD) or plasma vapor deposition (PVD) metal such as, for example, W, Al, Cu, and the like.
Thus, conventionally linear and circular patterns are defined by lithography and etching for the horizontal (HI) and vertical (VI) interconnect levels, respectively, and the vertical interconnect levels (VI) are limited to vias.
The resistance of metal lines is defined by height, width and resistivity. The height is often limited by arrays of smallest feature size (e.g., memory arrays). Due to capacitance and space minimization in these areas, the height of the metal lines is strongly limited. On the other hand, the use of lines with large line width leads to an increased chip size. Consequently, the resistance of metal lines is globally restricted to values which do not allow for high current densities due to Joule heating of highly, resistive lines.
Thus, power bus lines, designed to carry high current densities, and signal or equipotential lines that do not allow a large potential gradient along the line, are typically designed on an additional metal level using a thicker metal height, or using broad or parallel lines on thin metal levels, thereby increasing chip size.
Hence, if thicker metal lines are desired for increased current capacity (and thus higher bus speeds for example), then the conventional techniques for producing thick metal lines include increasing the thickness of the metal layer and increasing the number of metal layers, each of which increases chip size and processing steps.
Moreover, for a given combination of conducting and insulating materials, the only way to significantly reduce the capacitance of metal lines with narrow spacing is to make the metal stack sufficiently thin. Similarly, low resistance lines are produced by increasing their thickness accordingly. However, conventionally, both characteristics cannot be united on one metal level.
In a typical multi-layer metallization sequence, thin metal layers (e.g., bitline levels for DRAMs) are built first and then thick ones are built last. Consequently, the first metal levels are not useful for low resistance requirements. This has resulted in a significant limitation for a chip-size-optimized interconnect design. Moreover, the tradeoff between low capacitance and low resistance requirements is enhanced when the number of thin metal layers is increased as proposed recently for multiple bitline architectures.